1. Field of the Invention
The present invention relates to a semiconductor device and a method for producing same. More particularly, it relates to a semiconductor device having a memory structure suitable for a high degree of integration and a method for producing same.
2. Description of the Related Art
Recently, in a semiconductor device having a memory structure with a capacitor, for example, a Dynamic Random Access Memory (DRAM), various structures have been proposed by which the degree of integration can be increased.
An increase of a degree of integration of a planar type DRAM has been limited, and thus, to increase the degree of integration, a tertiary structure has been developed.
A stacked type or trench type structure are well known tertiary structures but an increase of the degree of integration of the stacked type capacitor is also limited, and therefore, the trench type capacitor is widely used at present as a DRAM capacitor.
FIG. 1 is a conventional example in which trench type capacitors are provided with a LOCUS type isolation therebetween.
In FIG. 1, a p.sup.+ silicon layer 2, n.sup.+ silicon region, n.sup.+ silicon regions source-drain and a trench capacitor 9 are formed on a p type substrate 1. The trench capacitor is formed by the n.sup.+ silicon layer, an SiO.sub.2 layer 7 and a first polycrystalline silicon layer 3. Further, a second polycrystalline silicon layer 5 acts as a bit line, and an aluminum layer 6 and a polycide layer 4 act as word lines.
In the DRAM shown in FIG. 1, when the size of the DRAM is miniaturized, to increase the degree of integration, the element isolation effect is reduced and a leak is generated between the trench capacitors 9, and the source and drain regions (n.sup.+ silicon regions).
FIG. 2 shows another conventional example, which is an improvement of the conventional device shown in FIG. 1. In FIG. 2, to prevent the leakage between the trench capacitors, isolation between the trench capacitors 9 is also provided by forming a trench. In the structure of FIG. 2, the leakage between the trench capacitors is prevented, but to increase the degree of integration, the depth of the trench capacitor must be increased, and the process for increasing the depth of the trench capacitor is very difficult. In FIG. 2, 8 is a transfer gate, 10 is a silicon substrate, 11 is an isolation trench, 12 is a polycrystalline silicon layer (cell plate), 13 is a polycrystalline silicon layer, 14 is a capacitor insulating layer of, for example, SiO.sub.2 and 15 is a silicon nitride layer.
FIG. 3 shows a conventional isolation merged vertical capacitor (IVEC) cell type structure in which a capacitor is formed at both sides of an isolation trench, and a cell plate is formed in the same trench. Nevertheless, if this structure is further miniaturized, the capacitance becomes small, and thus the depth of the trench must be increased to increase the capacitance, and as explained above, the process for increasing the depth of the trench is difficult.
The reference numbers used in FIG. 3, which are the same as those used in FIGS. 1 and 2, denote the same elements. This holds true throughout the remaining Figures.